Electronic circuits, such as integrated microcircuits, are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microcircuit devices typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of microcircuit being designed, its complexity, the design team, and the microcircuit fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware “tools” will verify a design at various stages of the design flow by running software simulators and/or hardware emulators, and errors in the design are corrected.
Several steps are common to most design flows. Initially, the specification for the new microcircuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit is described in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). The logic of the circuit is then analyzed, to confirm that the logic incorporated into the design will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”
After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices (such as transistors, resistors, and capacitors) that will be used in the circuit, along with their interconnections. This logical generally corresponds to the level of representation displayed in conventional circuit diagrams. Preliminary timing estimates for portions of the circuit may be made at this stage, using an assumed characteristic speed for each device. In addition, the relationships between the electronic devices are analyzed, to confirm that the circuit described by the device design will correctly perform the functions desired for the circuit. This analysis is sometimes referred to as “formal verification.”
Once the relationships between circuit devices have been established, the design is again transformed, this time into a physical design that describes specific geometric elements. This type of design often is referred to as a “layout” design. The geometric elements define the shapes that will be created in various materials to actually manufacture the circuit device components (e.g., contacts, channels, gates, etc.) making up the circuit. While the geometric elements are typically polygons, other shapes, such as circular and elliptical shapes, may be employed. These geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Geometric elements also are added to form the connection lines that will interconnect these circuit devices. Layout tools (often referred to as “place and route” tools), such as IC Station available from Mentor Graphics® Corporation of Wilsonville, Oreg. or Virtuoso available from Cadence® Design Systems of San Jose, Calif., are commonly used for both of these tasks.
With a layout design, each physical layer of the microcircuit will have a corresponding layer representation in the layout design data, and the geometric elements described in a layer representation will define the relative locations of the circuit device components that will make up a circuit device. Thus, the geometric elements in the representation of an implant layer will define the regions where doping will occur, while the geometric elements in the representation of a metal layer may define the locations in a metal layer where conductive wires will be formed to connect the circuit devices. Typically, a designer will perform a number of analyses on the layout design. For example, the layout design may be analyzed to confirm that it accurately represents the circuit devices and their relationships described in the device design. The layout design also may be analyzed to confirm that it complies with various design requirements, such as minimum spacings between geometric elements. Still further, it may be modified to include the use of redundant or other compensatory geometric elements intended to counteract limitations in the manufacturing process, etc. This analysis is sometimes referred to as “physical verification.”
After the layout design has been finalized, then it is converted into a format that can be employed by a mask or reticle writing tool to create a mask or reticle for use in a photolithographic manufacturing process. Masks and reticles are typically made using tools that expose a blank reticle to an electron or laser beam. Most mask writing tools are able to only “write” certain kinds of polygons, however, such as right triangles, rectangles or other trapezoids. Moreover, the sizes of the polygons are limited physically by the maximum beam aperture size available to the tool. Accordingly, larger geometric elements in the layout design, or geometric elements that are not basic right triangles, rectangles or trapezoids (which typically is a majority of the geometric elements in a layout design) must be “fractured” into the smaller, more basic polygons that can be written by the mask or reticle writing tool.
Once the layout design has been fractured, then the layout design data can be converted to a format compatible with the mask or reticle writing tool. Examples of such formats are MEBES, for raster scanning machines manufactured by ETEC, an Applied Materials Company, the “.MIC” format from Micronics AB in Sweden, and various vector scan formats for Nuflare, JEOL, and Hitachi machines, such as VSB12 or VSB12. The written masks or reticles can then be used in a photolithographic process to expose selected areas of a wafer in order to produce the desired integrated circuit devices on the wafer.
To meet the demand for more powerful microdevices, designers have regularly increased the average density of their structures. For example, the area of an integrated circuit that might once have contained 100 transistors may now be required to contain 1,000 or even 10,000 transistors. Some current microdevice designs call for microdevice structures to be packed so closely that it may be difficult to properly manufacture adjacent structures in a single lithographic process. For example, a current microcircuit design may specify a series of parallel conductive lines positioned so closely that a conventional mask writer cannot resolve the pitch between the lines.
To address this issue, the structures in a layer of a microcircuit device are now sometimes formed using two or more separate lithographic processes. This technique, referred to as “double patterning,” partitions a layout design into two or more groups or “colors,” each of which is then used to form a complementary lithographic mask pattern. Thus, if a layout design calls for a series of closely-spaced parallel connective lines, this target pattern may be partitioned so that adjacent lines are actually formed by different masks in separate lithographic processes.
While double patterning lithographic techniques allow for denser microdevice structures, it is sometimes difficult to implement these techniques. For example, it may difficult to determine when the geometric elements described in layout design data (corresponding to the physical structures of the microdevice) can be correctly partitioned into two complementary sets of layout design data without creating a conflict (i.e., a situation where two or more adjacent geometric elements are too close to be formed by the same lithographic mask, but are nonetheless scheduled to be formed by the same lithographic mask).